Input/Output and Exception Handling on the WC34020 -- Processing Traps and Interrupts

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Processing Traps and Interrupts

An attempt to execute an illegal instruction (such as as instruction with an unrecognized operation code or a divide by zero) on the WC34020 causes a trap. When a trap occurs, the processor transfers control from the current instruction to an instruction whose address is specified by a trap vector in memory. The interrupts associated with input/ouput events cause similar transfers of control. The interrupts that may occur on the WC34020 are partitioned into groups according to the priorities of the devices that requested them. That is, there is one group of interrupts for priority 1 devices (terminals), one for priority 2 devices (disks) and one group for priority 3 devices (the timer). Thus, there are a total of four distinct groups of exceptional conditions or exceptions handled by the machine.

In the high end of the WC34020's memory there are 4 pairs of words used to specify how interrupts should be handled. One pairs is associated with each of the 4 classes of exceptions just described. The pair associated with traps is called the trap vector. The pairs associated with interrupts are called interrupt vectors. The first word in each pair is used as the address of the handler routine that should be invoked when the corresponding exception occurs. Before this routine is invoked, the value in the second word of the trap or interrupt vector is loaded into the processor status register.

When a trap or interrupt handler is invoked, the processor essentially executes a CALL passing two parameters to the handler. A 3 word frame is allocated on the stack. The layout of an exception hander frame is shown in the figure below.

Layout of Exception Handler Stack Frame

The stack pointer register (A7) is adjusted to point to the last word of the frame (the trap or interrupt handler will typically execute a LINK instruction once it gets control to save and update the frame pointer register (A6) and decrement the stack pointer to make room for any local variables). The previous value of the PC register is stored in the last word of the frame as in a normal call. In addition, the value of the processor status register from before the exception is stored in the location normally reserved for the first parameter to a procedure. Finally, a code indicating the cause of the exception is stored in the word that would usually hold a procedure's second parameter.

The meaning of the code passed to an exception handler depends on the type of exception involved. For all interrupts, the code passed is the address in memory of the device register associated with the completion that causeed the interrupt. For an input completion on a terminal, this will be the address of the terminal's input buffer register. For an output completion, the address of the associated output buffer register will be passed. For timer interrupts, the address of the timer status register is used. Finally, for traps, the following codes are used.

The operation code found in the word pointed to by the program counter was not the code for any known instruction.
An illegal addressing mode was used in an instruction (for example, an attempt to execute an LEA instruction with two data registers as arguments would cause such a trap).
The divisor in a DIVS instruction was zero.

The major difference between the invocation of an exception handler and a regular CALL is that the arguments are pushed onto the stack as part of exception processing, while they must be pushed onto the stack by separate instructions that precede a normal call.