The processor status register is actually divided into two parts. The low order 8 bits of the register are used to store the processor's priority. The high order bits are used to store the machine's condition code bits.
Before each instruction's execution, the processor checks to see if there are interrupt requests pending. Each interrupt request has a priority value associated with it equal to the priority of the device that made the request. If there is no interrupt pending whose priority exceeds the priority value currently stored in the processor status register, execution of the next instruction proceeds normally. If there are one or more interrupts whose priorities exceed the current processor priority, the system grants the interrupt request with the highest priority. Within a priority level interrupt requests are processed on a first come first served basis.
The priority value in the processor status register may be changed in one of two ways. The WC34020 instruction set includes a LDPS (Load Processor Status) instruction which can be used to put a new value in the process status register. The instruction takes a single memory location as an argument and loads the contents of that location into the processor status register. The processor status register is also changed when the machine processes an interrupt request or a trap. The condition code bits in the processor status register are changed in all these cases and when a CMP instruction is executed.