The first of these three words is the device status register. The second word is the input buffer register. The third word is the output buffer register.
Layout of Terminal Device Registers
The diagram of the device registers shows how the bits of the device status register are used. All but the four bits which are not marked with dash lines are unused. The low order bit (bit 15), referred to as DEVINTEN in the figure, determines whether or not the terminal should request an interrupt when a completion occurs. If this bit's value is 1 when either an input or output event completes, the device will request an interrupt. This bit's value can be set by storing an appropriate value to the location in memory associated with the device status register. When such a store occurs, only the DEVINTEN bit of the status register is changed.
Bit 14, referred to as DEVBUSY in the diagram, indicates whether the device is currently busy printing a character. Its value is 1 whenever the device is busy. Bit 13, referred to as INPUTRDY in the figure indicates whether a new input character is available in the input buffer register. Finally, bit 11, referred to as OVERRUN in the figure, is set to 1 when a new input character arrives before the previous character is read from the input buffer register. That is, a value of 1 in this bit indicates that an input character has been lost.
Input characters received by the terminal are made available to the running program through the input buffer register. When the INPUTRDY bit of the status register for a terminal is 1, the program can obtain the next character by simply loading its value from the location in memory associated with this register. Loading a value from this word has several side effects. If the interrupt request made when the character in the buffer arrived is still pending, it is cleared when a read from the buffer occurs. In all cases, a read from the input buffer clears the INPUTRDY and OVERRUN bits in the associated status register. A store to this buffer has no effect.
Characters are printed by storing them in the output buffer register. When such a store occurs, the DEVBUSY bit in the corresponding status register is set and an output operation is started. Stores to this location should not be performed while the DEVBUSY bit is set. Such stores will have no effect.
If the DEVINTEN bit is 1, an interrupt will be requested whenever an input character arrives or an output operation completes. If events of both sorts occur before the interrupt requested for the first event is granted by the processor, two separate interrupts will be requested. On the other hand, if two completions of the same sort occur before the interrupt requested for the first event is granted, only a single interrupt will occur for the two events. Note, that the interrupt mechanism described below provides no way to distinguish an interrupt resulting from an input completion from one resulting from an output completion.